BEFORE — The industry's yield rule

@thedataandaiguy

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Cerebras WSE-3

Why it worked

The video effectively explains a complex technical concept (chip manufacturing yield) using clear visuals and a narrative that highlights a groundbreaking solution (Cerebras WSE-3). It appeals to a niche audience interested in technology and innovation by showcasing a product that challenges industry norms.

Summary

The video explains the traditional "yield rule" in chip manufacturing where defects on a wafer lead to discarding entire dies, limiting chip size. It then introduces Cerebras' WSE-3, which treats the entire wafer as a single chip, using fabric to route around defective cores and enabling massive scale and speed.

Structure

1Introduction to the old yield rule
2Explanation of how Cerebras WSE-3 works
3Details on WSE-3's scale and features
4Comparison with traditional chiplet designs
5The payoff: monolithic wafer design and its benefits

Product placement

The video prominently features and explains the Cerebras WSE-3 chip, detailing its architecture, capabilities, and how it differs from traditional chip manufacturing methods. The entire video is focused on this product.

Original caption

Cerebras builds a single chip the size of a dinner plate — 8 inches by 8 inches, 4 trillion transistors, 900,000 cores. The WSE-3 keeps the entire wafer intact and routes around any defective core instead of dicing it into hundreds of small chips. #techtok #hereswhatyouneedtoknow #cerebras #waferscale #LearnOnTikTok

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On-screen text

BEFORE — The industry's yield rule 300 mm silicon wafer die (<800 mm^2) wafer diced into hundreds of chips defect -> discarded (one defect kills the die) OLD RULE: max yieldable die ~800 mm bigger die -> yield collapses HOW — WSE-3: the whole wafer IS the chip WSE-3 die ~46,000 mm^2 of active silicon (~8 in x 8 in, dinner-plate scale) 900,000 cores + on-chip fabric between them defective core disabled fabric routes fabric routes around the defect (built-in redundancy) 4 trillion transistors 44 GB on-chip SRAM one monolithic die AMD chiplet route — modular, off-die links (slower) Cerebras — monolithic wafer, on-chip speeds Cerebras — monolithic wafer, on-chip speeds THE PAYOFF — Everything stays on one piece of silicon WSE-3 (single die) core <-> core on-chip fabric — nanosecond hops 4,000,000,000,000 transistors · 900,000 cores 44 GB SRAM speed bar same signal, orders of magnitude closer on-chip (WSE-3) off-chip link (traditional multi-chip) The industry's yield assumption

Transcript

BEFORE — The industry's yield rule 300 mm silicon wafer wafer diced into hundreds of chips die (<800 mm^2) defect -> discarded (one defect kills the die) OLD RULE: max yieldable die ~800 mm bigger die -> yield collapses HOW — WSE-3: the whole wafer IS the chip WSE-3 die ~46,000 mm^2 of active silicon (~8 in x 8 in, dinner-plate scale) 900,000 cores + on-chip fabric between them defective core disabled fabric routes fabric routes around the defect (built-in redundancy) 4 trillion transistors 44 GB on-chip SRAM one monolithic die AMD chiplet route — modular, off-die links (slower) Cerebras — monolithic wafer, on-chip speeds Cerebras — monolithic wafer, on-chip speeds THE PAYOFF — Everything stays on one piece of silicon WSE-3 (single die) core <-> core on-chip fabric — nanosecond hops 4,000,000,000,000 transistors · 900,000 cores 44 GB SRAM speed bar same signal, orders of magnitude closer on-chip (WSE-3) off-chip link (traditional multi-chip) The industry's yield assumption